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EDMA3 Registers
11.4.1.4.2 Queue Status Registers (QSTATn)
The queue status registers (QSTATn) is shown in Figure 11-63 and described in Table 11-47.
Figure 11-63. Queue Status Register n (QSTATn)
31 25 24 23 21 20 16
Reserved THRXCD Reserved WM
R-0 R-0 R-0 R-0
15 13 12 8 7 4 3 0
Reserved NUMVAL Reserved STRTPTR
R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-47. Queue Status Register n (QSTATn) Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
24 THRXCD Threshold exceeded. THRXCD is cleared by writing a 1 to the corresponding QTHRXCDn bit in
the EDMA3CC error clear register (CCERRCLR).
0 Threshold specified by the Qn bit in the queue watermark threshold A register (QWMTHRA) has
not been exceeded.
1 Threshold specified by the Qn bit in the queue watermark threshold A register (QWMTHRA) has
been exceeded.
23-21 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
20-16 WM 0-10h Watermark for maximum queue usage. Watermark tracks the most entries that have been in
queue n since reset or since the last time that the watermark (WM) bit was cleared. WM is cleared
by writing a 1 to the corresponding QTHRXCDn bit in the EDMA3CC error clear register
(CCERRCLR).
0-10h Legal values are 0 (empty) to 10h (full).
11h-1Fh Reserved.
15-13 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
12-8 NUMVAL 0-10h Number of valid entries in queue n. The total number of entries residing in the queue manager
FIFO at a given instant. Always enabled.
0-10h Legal values are 0 (empty) to 10h (full).
11h-1Fh Reserved.
7-4 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
3-0 STRTPTR 0-Fh Start pointer. The offset to the head entry of queue n, in units of entries. Always enabled. Legal
values are 0 (0th entry) to Fh (15th entry).
961
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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