www.ti.com
Ethernet Subsystem Registers
14.5.9.33 C2_RX_IMAX Register (offset = 80h) [reset = 0h]
C2_RX_IMAX is shown in Figure 14-229 and described in Table 14-247.
SUBSYSTEM CORE 2 RECEIVE INTERRUPTS PER MILLISECOND
Figure 14-229. C2_RX_IMAX Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved C2_RX_IMAX
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-247. C2_RX_IMAX Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
5-0 C2_RX_IMAX R/W 0h Core 2 Receive Interrupts per Millisecond - The maximum number of
interrupts per millisecond generated on C2_RX_PULSE if pacing is
enabled for this interrupt.
1471
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
