Ethernet Subsystem Registers
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14.5.5.1 TX0_HDP Register (offset = A00h) [reset = 0h]
TX0_HDP is shown in Figure 14-89 and described in Table 14-103.
CPDMA_STATERAM TX CHANNEL 0 HEAD DESC POINTER *
Figure 14-89. TX0_HDP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_HDP
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-103. TX0_HDP Register Field Descriptions
Bit Field Type Reset Description
31-0 TX_HDP R/W 0h TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA
Buffer Descriptor address to a head pointer location initiates TX
DMA operations in the queue for the selected channel.
Writing to these locations when they are non-zero is an error (except
at reset).
Host software must initialize these locations to zero on reset.
1324
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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