USB Registers
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16.5.4.3 DLLHS_2 Register (offset = 8h) [reset = 1Fh]
DLLHS_2 is shown in Figure 16-136 and described in Table 16-147.
the 2nd DLLHS control register. bits 4:0 are unrelated to the DLLHS and are linestate filter settings
Figure 16-136. DLLHS_2 Register
31 30 29 28 27 26 25 24
DLLHS_CNTRL_LDO
R/W-0h
23 22 21 20 19 18 17 16
DLLHS_STATUS_LDO
R-0h
15 14 13 12 11 10 9 8
Reserved
R/W-0h
7 6 5 4 3 2 1 0
Reserved LINESTATE_DEBOU LINESTATE_DEBOUNCE_CNTL
NCE_EN
R/W-0h R/W-1h R/W-Fh
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-147. DLLHS_2 Register Field Descriptions
Bit Field Type Reset Description
31-24 DLLHS_CNTRL_LDO R/W 0h
See DFT spec for details
23-16 DLLHS_STATUS_LDO R 0h
See DFT spec for details
15-5 Reserved R/W 0h
4 LINESTATE_DEBOUNCE R/W 1h
Enables the linestate debounce filter
_EN
3-0 LINESTATE_DEBOUNCE R/W Fh
Used for control of the linestate debounce filter when going from
_CNTL
syncronous to async linestate.
1906
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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