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7.3.5.32 RDWR_LVL_CTRL Register (offset = DCh) [reset = 0h]
Read-Write Leveling Control Register
Read-Write Leveling Control Register is shown in Figure 7-122 and described in Table 7-142.
Read-Write Leveling Control Register
Figure 7-122. Read-Write Leveling Control Register
31 30 29 28 27 26 25 24
REG_RDWRLVLFULL REG_RDWRLVLINC_PRE
_START
R/W-
23 22 21 20 19 18 17 16
REG_RDLVLINC_INT
R/W-
15 14 13 12 11 10 9 8
REG_RDLVLGATEINC_INT
R/W-
7 6 5 4 3 2 1 0
REG_WRLVLINC_INT
R/W-
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-142. Read-Write Leveling Control Register Field Descriptions
Bit Field Type Reset Description
31 REG_RDWRLVLFULL_S R/W Full leveling trigger.
TART Writing a 1 to this field triggers full read and write leveling.
This bit will self-clear to 0.
30-24 REG_RDWRLVLINC_PR Incremental leveling pre-scalar in number of refresh periods.
E The value programmed is minus one the required value.
Refresh period is defined by reg_refresh_rate in SDRAM Refresh
Control register.
23-16 REG_RDLVLINC_INT R/W Incremental read data eye training interval.
Number of reg_rdwrlvlinc_pre intervals between incremental read
data eye training.
A value of 0 will disable incremental read data eye training.
15-8 REG_RDLVLGATEINC_I R/W Incremental read DQS gate training interval.
NT Number of reg_rdwrlvlinc_pre intervals between incremental read
DQS gate training.
A value of 0 will disable incremental read DQS gate training.
7-0 REG_WRLVLINC_INT R/W Incremental write leveling interval.
Number of reg_rdwrlvlinc_pre intervals between incremental write
leveling.
A value of 0 will disable incremental write leveling.
457
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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