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Power, Reset, and Clock Management
8.1.12.2.26 CM_SSC_MODFREQDIV_DPLL_CORE Register (offset = 64h) [reset = 0h]
CM_SSC_MODFREQDIV_DPLL_CORE is shown in Figure 8-109 and described in Table 8-117.
Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique by defining it as a ratio
of DPLL_REFCLK/4 Fm = [DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV =
MODFREQDIV_MANTISSA * 2^MODFREQDIV_EXPONENT [warm reset insensitive]
Figure 8-109. CM_SSC_MODFREQDIV_DPLL_CORE Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved MODFREQDIV_EXPONENT
R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved MODFREQDIV_MANTISSA
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-117. CM_SSC_MODFREQDIV_DPLL_CORE Register Field Descriptions
Bit Field Type Reset Description
31-11 Reserved R 0h
10-8 MODFREQDIV_EXPONE R/W 0h
Set the Exponent component of MODFREQDIV factor
NT
7 Reserved R 0h
6-0 MODFREQDIV_MANTISS R/W 0h
Set the Mantissa component of MODFREQDIV factor
A
641
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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