Texas Instruments AM335 Series Technical Reference Manual

www.ti.com DMTimer
20.1.5.7 IRQENABLE_CLR Register (offset = 30h) [reset = 0h]
IRQENABLE_CLR is shown in Figure 20-15 and described in Table 20-17.
Component interrupt request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding
_SET register.
Figure 20-15. IRQENABLE_CLR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TCAR_EN_FLAG OVF_EN_FLAG MAT_EN_FLAG
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-17. IRQENABLE_CLR Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 TCAR_EN_FLAG R/W 0h
IRQ enable for Capture
0x0x0(W) = No action
0x0x0(R) = IRQ event is disabled
0x0x1(W) = Clear IRQ enable
0x0x1(R) = IRQ event is enabled
1 OVF_EN_FLAG R/W 0h
IRQ enable for Overflow
0x0x0(W) = No action
0x0x0(R) = IRQ event is disabled
0x0x1(W) = Clear IRQ enable
0x0x1(R) = IRQ event is enabled
0 MAT_EN_FLAG R/W 0h
IRQ enable for Match
0x0x0(W) = No action
0x0x0(R) = IRQ event is disabled
0x0x1(W) = Clear IRQ enable
0x0x1(R) = IRQ event is enabled
3573
SPRUH73H–October 2011–Revised April 2013 Timers
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated

Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English