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USB Registers
16.5.1.6 IRQCLEARR Register (offset = 30h) [reset = 0h]
IRQCLEARR is shown in Figure 16-27 and described in Table 16-35.
Figure 16-27. IRQCLEARR Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved RX_PKT_CMP_1 TX_PKT_CMP_1 RX_PKT_CMP_0 TX_PKT_CMP_0
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved PD_CMP_FLAG RX_MOP_STARVATI RX_SOP_STARVATI
ON ON
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-35. IRQCLEARR Register Field Descriptions
Bit Field Type Reset Description
11 RX_PKT_CMP_1 R/W 0h
Interrupt enable for USB1 Rx CPPI DMA packet completion status
10 TX_PKT_CMP_1 R/W 0h
Interrupt enable for USB1 Tx CPPI DMA packet completion status
9 RX_PKT_CMP_0 R/W 0h
Interrupt enable for USB0 Rx CPPI DMA packet completion status
8 TX_PKT_CMP_0 R/W 0h
Interrupt enable for USB0 Tx CPPI DMA packet completion status
2 PD_CMP_FLAG R/W 0h
Interrupt enable when the packet is completed, the differ bits is set,
and the Packet Descriptor is pushed into the queue manager
1 RX_MOP_STARVATION R/W 0h Interrupt enable when queue manager cannot allocate an Rx buffer
in the middle of a packet.
0 RX_SOP_STARVATION R/W 0h Interrupt enable when queue manager cannot allocate an Rx buffer
at the start of a packet.
USBSS IRQ_ENABLE_CLR Register
1767
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
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