Ethernet Subsystem Registers
www.ti.com
14.5.6.48 P2_RX_DSCP_PRI_MAP3 Register (offset = 23Ch) [reset = 0h]
P2_RX_DSCP_PRI_MAP3 is shown in Figure 14-168 and described in Table 14-183.
CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3
Figure 14-168. P2_RX_DSCP_PRI_MAP3 Register
31 30 29 28 27 26 25 24
Reserved PRI31 Reserved PRI30
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved PRI29 Reserved PRI28
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved PRI27 Reserved PRI26
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved PRI25 Reserved PRI24
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-183. P2_RX_DSCP_PRI_MAP3 Register Field Descriptions
Bit Field Type Reset Description
30-28 PRI31 R/W 0h Priority
31 - A packet TOS of 0d31 is mapped to this received packet
priority.
26-24 PRI30 R/W 0h Priority
30 - A packet TOS of 0d30 is mapped to this received packet
priority.
22-20 PRI29 R/W 0h Priority
29 - A packet TOS of 0d39 is mapped to this received packet
priority.
18-16 PRI28 R/W 0h Priority
28 - A packet TOS of 0d28 is mapped to this received packet
priority.
14-12 PRI27 R/W 0h Priority
27 - A packet TOS of 0d27 is mapped to this received packet
priority.
10-8 PRI26 R/W 0h Priority
26 - A packet TOS of 0d26 is mapped to this received packet
priority.
6-4 PRI25 R/W 0h Priority
25 - A packet TOS of 0d25 is mapped to this received packet
priority.
2-0 PRI24 R/W 0h Priority
24 - A packet TOS of 0d24 is mapped to this received packet
priority.
1406
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
