Power, Reset, and Clock Management
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8.1.13.5.1 PRM_RSTCTRL Register (offset = 0h) [reset = 0h]
PRM_RSTCTRL is shown in Figure 8-179 and described in Table 8-198.
Global software cold and warm reset control. This register is auto-cleared. Only write 1 is possible. A read
returns 0 only.
Figure 8-179. PRM_RSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved RST_GLOBAL_COLD RST_GLOBAL_WAR
_SW M_SW
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-198. PRM_RSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 RST_GLOBAL_COLD_S R/W 0h Global COLD software reset control.
W This bit is reset only upon a global cold source of reset.
Read returns 0.
0x0 = 0x0 : Global COLD software reset is cleared.
0x1 = 0x1 : Asserts a global COLD software reset. The software
must ensure the SDRAM is properly put in sef-refresh mode before
applying this reset.
0 RST_GLOBAL_WARM_S R/W 0h Global WARM software reset control.
W This bit is reset upon any global source of reset (warm and cold).
Read returns 0.
0x0 = 0x0 : Global warm software reset is cleared.
0x1 = 0x1 : Asserts a global warm software reset.
726
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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