UART Registers
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19.5.1.28 Supplementary Status Register (SSR)
The supplementary status register (SSR) is shown in Figure 19-61 and described in Table 19-59.
NOTE: Bit 1 is reset only when SCR[4] is reset to 0.
Figure 19-61. Supplementary Status Register (SSR)
15 8
Reserved
R-0
7 3 2 1 0
Reserved DMACOUNTERRST RXCTSDSRWAKEUPSTS TXFIFOFULL
R-0 R/W-1 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-59. Supplementary Status Register (SSR) Field Descriptions
Bit Field Value Description
15-3 Reserved 0 Reserved.
2 DMACOUNTERRST 0 The DMA counter will not be reset, if the corresponding FIFO is reset (via FCR[1] or
FCR[2]).
1 The DMA counter will be reset, if the corresponding FIFO is reset (via FCR[1] or
FCR[2]).
1 RXCTSDSRWAKEUPSTS Pin falling edge detection: Reset only when SCR[4] is reset to 0.
0 No falling-edge event on RX, CTS, and DSR.
1 A falling edge occurred on RX, CTS, or DSR.
0 TXFIFOFULL 0 TX FIFO is not full.
1 TX FIFO is full.
3530
Universal Asynchronous Receiver/Transmitter (UART) SPRUH73H–October 2011–Revised April 2013
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