McASP Registers
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22.4.1.4 Pin Direction Register (PDIR)
The pin direction register (PDIR) specifies the direction of AXRn, ACLKX, AHCLKX, AFSX, ACLKR,
AHCLKR, and AFSR pins as either an input or an output pin. The PDIR is shown in Figure 22-42 and
described in Table 22-15.
Regardless of the pin function register (PFUNC) setting, each PDIR bit must be set to 1 for the specified
pin to be enabled as an output and each PDIR bit must be cleared to 0 for the specified pin to be an input.
For example, if the McASP is configured to use an internally-generated bit clock and the clock is to be
driven out to the system, the PFUNC bit must be cleared to 0 (McASP function) and the PDIR bit must be
set to 1 (an output).
When AXRn is configured to transmit, the PFUNC bit must be cleared to 0 (McASP function) and the
PDIR bit must be set to 1 (an output). Similarly, when AXRn is configured to receive, the PFUNC bit must
be cleared to 0 (McASP function) and the PDIR bit must be cleared to 0 (an input).
CAUTION
Writing to Reserved Bits
Writing a value other than 0 to reserved bits in this register may cause improper
device operation.
Figure 22-42. Pin Direction Register (PDIR)
31 30 29 28 27 26 25 24
AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
23 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved AXR5 AXR4 AXR3 AXR2 AXR1 AXR0
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3832
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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