DCAN Registers
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23.4.4 BTR Register (offset = 0Ch) [reset = 2301h]
BTR is shown in Figure 23-22 and described in Table 23-17.
This register is only writable if CCE and Init bits in the CAN control register are set. The CAN bit time may
be programmed in the range of 8 to 25 time quanta. The CAN time quantum may be programmed in the
range of 1 to1024 CAN_CLK periods. With a CAN_CLK of 8 MHz and BRPE = 0x00, the reset value of
0x00002301 configures the DCAN for a bit rate of 500kBit/s.
Figure 23-22. BTR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved BRPE
R-0h R-0h
15 14 13 12 11 10 9 8
Reserved TSeg2 TSeg1
R-0h R/WP-2h R/WP-3h
7 6 5 4 3 2 1 0
SJW BRP
R/WP-0h R/WP-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-17. BTR Register Field Descriptions
Bit Field Type Reset Description
31-20 Reserved R 0h
19-16 BRPE R 0h Baud rate prescaler extension.
Valid programmed values are 0 to 15.
By programming BRPE the baud rate prescaler can be extended to
values up to 1024.
15 Reserved R 0h
14-12 TSeg2 R/WP 2h Time segment after the sample point.
Valid programmed values are 0 to 7.
The actual TSeg2 value which is interpreted for the bit timing will be
the programmed TSeg2 value + 1.
11-8 TSeg1 R/WP 3h Time segment before the sample point.
Valid programmed values are 1 to 15.
The actual TSeg1 value interpreted for the bit timing will be the
programmed TSeg1 value + 1.
7-6 SJW R/WP 0h Synchronization Jump Width.
Valid programmed values are 0 to 3.
The actual SJW value interpreted for the synchronization will be the
programmed SJW value + 1.
5-0 BRP R/WP 1h Baud rate prescaler.
Value by which the CAN_CLK frequency is divided for generating the
bit time quanta.
The bit time is built up from a multiple of this quanta.
Valid programmed values are 0 to 63.
The actual BRP value interpreted for the bit timing will be the
programmed BRP value + 1.
3930
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
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