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Ethernet Subsystem Registers
14.5.7.8 TX_PAUSE Register (offset = 1Ch) [reset = 0h]
TX_PAUSE is shown in Figure 14-180 and described in Table 14-196.
CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER
Figure 14-180. TX_PAUSE Register
31 30 29 28 27 26 25 24
tx_pausetimer
R-0h
23 22 21 20 19 18 17 16
tx_pausetimer
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-196. TX_PAUSE Register Field Descriptions
Bit Field Type Reset Description
31-16 tx_pausetimer R 0h TX Pause Timer Value - This field allows the contents of the transmit
pause timer to be observed (and written in test mode).
The transmit pause timer is loaded by a received (incoming) pause
frame, and then decremented, at slottime intervals, down to zero at
which time CPGMAC_SL transmit frames are again enabled.
15-0 Reserved R 0h
1421
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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