Silicon Revision Functional Differences and Enhancements
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1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register
See Section 9.3.54, vtp_ctrl Register.
PG1.0: VTP_CTRL.NCIN and VTP_CTRL.PCIN reset value is 0.
PG2.x: VTP_CTRL.NCIN and VTP_CTRL.PCIN reset value is 1.
1.2.9 Changed Default Value of RGMII Mode to No Internal Delay
See Section 9.3.31, gmii_sel Register and Errata Advisory 1.0.10.
PG1.0: RGMII1_IDMODE And RGMII2_IDMODE reset value is 0.
PG2.x: RGMII1_IDMODE And RGMII2_IDMODE reset value is 1.
1.2.10 Changed Default Value of RMII Clock Source
See Section 9.3.31, gmii_sel Register and Errata Advisory 1.0.18.
PG1.0: RMII1_IO_CLK_EN and RMII2_IO_CLK_EN reset value is 0.
PG2.x: RMII1_IO_CLK_EN and RMII2_IO_CLK_EN reset value is 1.
1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot
See Section 26.1.8.4, EMAC Boot Procedure and Errata Advisory 1.0.7.
PG1.0: Link speed is determined by CONTROL register bit 6 in the external ethernet PHY. Note that some
PHYs may not update this bit, as it is not necessary as described in the 802.3 specification.
PG2.x: Link speed is determined by reading the Auto-Negotiation Advertisement and Auto-Negotiation
Link Partner Base Page Ability registers in the external ethernet PHY.
1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants
See Section 9.3.50, efuse_sma Register.
PG1.0: EFUSE_SMA register value is not applicable. Value is always 0.
PG2.x: Added EFUSE_SMA description to distinguish package type and maximum ARM frequency of the
device.
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Introduction SPRUH73H–October 2011–Revised April 2013
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