Functional Description
www.ti.com
As long as SIdleAck is not asserted, if an event occurs, the module can still generate an interrupt or a
DMA request after IdleReq assertion. In this case, the module ignores the idle request and SIdleAck will
not get asserted: The system power manager will abort the power mode transition procedure. It is then the
responsibility of the system to de-assert IdleReq before attempting to access the module.
When SIdleAck is asserted, the module does not assert any new interrupt or DMA request.
24.3.7.2.2 Transition From Smart-Idle Mode to Normal mode
McSPI detects the end of the idle period when the idle request signal (IdleReq) is deasserted.
Upon IdleReq de-assertion, the module switches back to normal mode and de-asserts SIdleAck signal.
The module is fully operational.
24.3.7.2.3 Force-Idle Mode
Force-idle mode is enabled as follows:
• The bit SIdleMode of the register MCSPI_SYSCONFIG is cleared to “00” (Force Idle).
The force idle mode is an idle mode where McSPI responds unconditionally to the idle request by
asserting the SIdleAck signal and by deasserting unconditionally the interrupt and DMA request lines if
asserted.
The transition from normal mode to idle mode does not affect the interrupt event bits of the
MCSPI_IRQSTATUS register.
In force-idle mode, the module is supposed to be disabled at that time, so the interrupt and DMA
request lines are likely deasserted. OCP clock and SPI clock provided to McSPI can be switched off.
An idle request during an SPI data transfer can lead to an unexpected and unpredictable result, and is
under software responsibility.
Any access to the module in force idle mode will generate an error as long as the OCP clock is alive
and IdleReq is asserted.
The module exits the force idle mode when:
• The idle request signal (IdleReq) is de-asserted.
Upon IdleReq de-assertion, the module switches back to normal mode and de-asserts SIdleAck signal.
The module is fully operational. The interrupt and DMA request lines are optionally asserted a clock
cycle later.
24.3.8 System Test Mode
McSPI is in system test mode (SYSTEST) when the bit System_Test of the register MCSPI_MODULCTRL
is set.
The SYSTEST mode is used to check in a very simple manner the correctness of the system interconnect
either internally to interrupt handler, or power manager, or externally to SPI I/Os.
I/O verification can be performed in SYSTEST mode by toggling the outputs and capturing the logic state
of the inputs. (See MCSPI_SYST register definition in Section 24.4.1.6)
24.3.9 Reset
24.3.9.1 Internal Reset Monitoring
The module is reset by the hardware when an active-low reset signal, synchronous to the OCP interface
clock is asserted on the input pin RESETN.
This hardware reset signal has a global reset action on the module. All configuration registers and all state
machines are reset, in all clock domains.
Additionally, the module can be reset by software through the bit SoftReset of the register
MCSPI_SYSCONFIG. This bit has exactly the same action on the module logic as the hardware RESETN
signal. The register MCSPI_SYSCONFIG is not sensitive to software reset. The SoftReset control bit is
active high. The bit is automatically reset to 0 by the hardware.
4030
Multichannel Serial Port Interface (McSPI) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
