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Introduction
• Up to 8 QDMA Channels
– QDMA Channels are triggered automatically upon writing to PaRAM
– Support for programmable QDMA Channel to PaRAM mapping
• Up to 64 Event Inputs
• Up to 8 Interrupt outputs for multi-core support
• Up to 256 PaRAM entries
– Each PaRAM entry can be used as DMA Entry (up to 64), QDMA Entry (up to 8), or Link Entry
(remaining)
• 8 Priority Levels for mapping CC/TC priority relative to priority of other masters in the system.
• Up to 8 Event Queues
• 16 Event Entries per Event Queue
• Supports three-transfer dimensions
– A-synchronized transfers—one dimension serviced per event
– AB-synchronized transfers—two dimensions serviced per event
– Independent Indexes on Source and Destination
– Does not support direct submission of 3D transfer to TC
– Chaining feature allows 3D transfer based on single event
• Increment and FIFO transfer addressing modes (TC feature)
• Linking mechanism allows automatic PaRAM Entry update
• Transfer Completion Signaling between TC and CC for Chaining and Interrupt generation.
• Programmable assignment of Priority to TC channel.
• Proxied Memory Protection for TR submission
• Parameterizable support for Active Memory Protection for accesses to PaRAM and registers.
• Queue Watermarking
• Missed Event Detection
• Error and status recording to facilitate debug
• Single Clock domain for all interfaces
• Parameterizable number of Write Completion interfaces (up to 8) (set to number of TC Channels)
• AET Event generation
11.1.2.2 Unsupported TPCC Features
This device does not support AET event generation because output is not connected.
11.1.3 Third-Party Transfer Controller (TPTC) Overview
11.1.3.1 TPTC Features
The TPTC module includes the following features:
• Up to eight independent channels
• External event control use model (TPCC)
• Read and Write Master ports per Channel 64- or 128-bit configuration.
• Parameterizable FIFO size
• Up to four in-flight Transfer Requests
• Proxied Memory protection for data transfers
• Programmable Priority levels (up to 8)
• Background programmation capability
• Supports 2-dimensional transfers with independent indexes on Source and Destination.
871
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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