www.ti.com
EMIF
7.3.5.16 INT_CFG_VAL_1 Register (offset = 58h) [reset = 0h]
Interface Configuration Value 1 Register
Interface Configuration Value 1 Register is shown in Figure 7-106 and described in Table 7-126.
Figure 7-106. Interface Configuration Value 1 Register
31 30 29 28 27 26 25 24
REG_SYS_BUS_WIDTH Reserved
R-2 R-0
23 22 21 20 19 18 17 16
Reserved
R-0
15 14 13 12 11 10 9 8
REG_WR_FIFO_DEPTH
R-14
7 6 5 4 3 2 1 0
REG_CMD_FIFO_DEPTH
R-A
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-126. Interface Configuration Value 1 Register Field Descriptions
Bit Field Type Reset Description
31-30 REG_SYS_BUS_WIDTH R 2 L3 OCP data bus width for a particular configuration.
0 = 32 bit wide.
1 = 64 bit wide.
2 = 128 bit wide.
3 = 256 bit wide.
29-16 Reserved R 0
Reserved for future use.
15-8 REG_WR_FIFO_DEPTH R 0x14
Write Data FIFO depth for a particular configuration.
7-0 REG_CMD_FIFO_DEPTH R 0xA
Command FIFO depth for a particular configuration.
441
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
