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Enhanced Capture (eCAP) Module
15.3.4.1.5 CAP3 Register (offset = 10h) [reset = 0h]
CAP3 is shown in Figure 15-120 and described in Table 15-113.
Figure 15-120. CAP3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP3
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-113. CAP3 Register Field Descriptions
Bit Field Type Reset Description
31-0 CAP3 R/W 0h In CMP mode, this is a time-stamp capture register.
In APWM mode, this is the period shadow (APRD) register.
You update the PWM period value through this register.
In this mode, CAP3 shadows CAP1.
1639
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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