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7.3.6.5 DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register
(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 Write DQS Slave Ratio
Register(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) is shown in the figure and table below.
Table 7-154. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register
(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0h
15 10 9 0
Reserved WR_DQS_SLAVE_RATIO_CS0
R-0 W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-155. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register(
DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved 0 Reserved
19-10 Reserved Reserved
9-0 WR_DQS_SLAVE_R Ratio value for Write DQS slave DLL for CS0.
ATIO_CS0
This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in
units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by
this number over 256 to get the delay value for the slave delay line.
7.3.6.6 DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0)
The DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) is showin in the figure and table below.
Figure 7-133. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0
15 10 9 0
Reserved WRLVL_INIT_RATIO_CS0
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-156. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved 0 Reserved
19-10 Reserved 0h Reserved
9-0 WRLVL_INIT_RATIO 0h The user programmable init ratio used by Write Leveling FSM when
_CS0 DATA0/1_REG_PHY_WRLVL_INIT_MODE_0 register value set to 1
471
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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