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Functional Description
• 3h: Reserved.
During the smart-idle mode period, the MMC/SD/SDIO host controller acknowledges that the OCP and
Functional clocks may be switched off whatever the value set in the SD_SYSCONFIG[9:8]
CLOCKACTIVITY field.
18.3.3.3 Transition from Normal Mode to Smart-Idle Mode
Smart-idle mode is enabled when the SD_SYSCONFIG[4:3] SIDLEMODE bit field is set to 2h or 3h. The
MMC/SD/SDIO host controller goes into idle mode when the PRCM issues an idle request, according to
its internal activity. The MMC/SD/SDIO host controller acknowledges the idle request from the PRCM after
ensuring the following:
• The current multi/single-block transfer is completed.
• Any interrupt or DMA request is asserted.
• There is no card interrupt on the SD_dat1 signal.
As long as the MMC/SD/SDIO controller does not acknowledge the idle request, if an event occurs, the
MMC/SD/SDIO host controller can still generate an interrupt or a DMA request. In this case, the module
ignores the idle request from the PRCM.
As soon as the MMC/SD/SDIO controller acknowledges the idle request from the PRCM:
• If Smart-Idle mode the module does not assert any new interrupt or DMA request
18.3.3.4 Transition from Smart-Idle Mode to Normal Mode
The MMC/SD/SDIO host controller detects the end of the idle period when the PRCM deasserts the idle
request. For the wake-up event, there is a corresponding interrupt status in the SD_STAT register. The
MMC/SD/SDIO host controller operates the conversion between wake-up and interrupt (or DMA request)
upon exit from smart-idle mode if the associated enable bit is set in the SD_ISE register.
Interrupts and wake-up events have independent enable/disable controls, accessible through the
SD_HCTL and SD_ISE registers. The overall consistency must be ensured by software.
The interrupt status register SD_STAT is updated with the event that caused the wake-up in the CIRQ bit
when the SD_IE[8] CIRQ_ENABLE associated bit is enabled. Then, the wake-up event at the origin of the
transition from smart-idle mode to normal mode is converted into its corresponding interrupt or DMA
request. (The SD_STAT register is updated and the status of the interrupt signal changes.)
When the idle request from the PRCM is deasserted, the module switches back to normal mode. The
module is fully operational.
18.3.3.5 Force-Idle Mode
Force-idle mode is enabled when the SD_SYSCONFIG[4:3] SIDLEMODE bit field is cleared to 0. Force-
idle mode is an idle mode where the MMC/SD/SDIO host controller responds unconditionally to the idle
request from the PRCM. Moreover, in this mode, the MMC/SD/SDIO host controller unconditionally
deasserts interrupts and DMA request lines are asserted.
The transition from normal mode to force-idle mode does not affect the bits of the SD_STAT register. In
force-idle mode, the interrupt and DMA request lines are deasserted. Interface Clock (OCP) and functional
clock (CLKADPI) can be switched off.
CAUTION
In Force-idle mode, an idle request from the PRCM during a command or a
data transfer can lead to an unexpected and unpredictable result.
When the module is idle, any access to the module generates an error as long
as the OCP clock is alive.
3359
SPRUH73H–October 2011–Revised April 2013 Multimedia Card (MMC)
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