Ethernet Subsystem Registers
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14.5.2.7 CPDMA_SOFT_RESET Register (offset = 1Ch) [reset = 0h]
CPDMA_SOFT_RESET is shown in Figure 14-35 and described in Table 14-46.
CPDMA_REGS SOFT RESET REGISTER
Figure 14-35. CPDMA_SOFT_RESET Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved SOFT_RESET
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-46. CPDMA_SOFT_RESET Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 SOFT_RESET R/W 0h Software reset - Writing a one to this bit causes the CPDMA logic to
be reset.
Software reset occurs when the RX and TX DMA Controllers are in
an idle state to avoid locking up the VBUSP bus.
After writing a one to this bit, it may be polled to determine if the
reset has occurred.
If a one is read, the reset has not yet occurred.
If a zero is read then reset has occurred.
1264
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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