Enhanced PWM (ePWM) Module
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15.2.4.3.1 Action-Qualifier Output A Control Register (AQCTLA)
The action-qualifier output A control register (AQCTLA) is shown in Figure 15-78 and described in
Table 15-70.
Figure 15-78. Action-Qualifier Output A Control Register (AQCTLA)
15 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CBD CBU CAD CAU PRD ZRO
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-70. Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions
Bits Name Value Description
15-12 Reserved 0 Reserved
11-10 CBD 0-3h Action when the time-base counter equals the active CMPB register and the counter is decrementing.
0 Do nothing (action disabled)
1h Clear: force EPWMxA output low.
2h Set: force EPWMxA output high.
3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
9-8 CBU 0-3h Action when the counter equals the active CMPB register and the counter is incrementing.
0 Do nothing (action disabled)
1h Clear: force EPWMxA output low.
2h Set: force EPWMxA output high.
3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
7-6 CAD 0-3h Action when the counter equals the active CMPA register and the counter is decrementing.
0 Do nothing (action disabled)
1h Clear: force EPWMxA output low.
2h Set: force EPWMxA output high.
3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
5-4 CAU 0-3h Action when the counter equals the active CMPA register and the counter is incrementing.
0 Do nothing (action disabled)
1h Clear: force EPWMxA output low.
2h Set: force EPWMxA output high.
3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
3-2 PRD 0-3h Action when the counter equals the period.
Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0
or counting down.
0 Do nothing (action disabled)
1h Clear: force EPWMxA output low.
2h Set: force EPWMxA output high.
3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
1-0 ZRO 0-3h Action when counter equals zero.
Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or
counting up.
0 Do nothing (action disabled)
1h Clear: force EPWMxA output low.
2h Set: force EPWMxA output high.
3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
1590
Pulse-Width Modulation Subsystem (PWMSS) SPRUH73H–October 2011–Revised April 2013
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