Coarse-grain
scheduler
Prog. data
sequencer
Data master
selector
Vertex data
master
Pixel data
master
General-purpose
data master
Universal
scalable
shader
engine
(USSE)
Tiling
coprocessor
Pixel
coprocessor
Multilevel cache
Texturing coprocessor
Power
management
control
register
block
SOCIF
BIF
L3 interconnectL3 interconnect
POWERVR
SGX530
sgx-003
MMU
Functional Description
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5.3 Functional Description
5.3.1 SGX Block Diagram
The SGX subsystem is based on the POWERVR® SGX530 core from Imagination Technologies. The
architecture uses programmable and hard coded pipelines to perform various processing tasks required in
2D, 3D, and video processing. The SGX architecture comprises the following elements:
• Coarse grain scheduler
– Programmable data sequencer (PDS)
– Data master selector (DMS)
• Vertex data master (VDM)
• Pixel data master (PDM)
• General-purpose data master
• USSE
• Tiling coprocessor
• Pixel coprocessor
• Texturing coprocessor
• Multilevel cache
Figure 5-2 shows a block diagram of the SGX cores.
Figure 5-2. SGX Block Diagram
5.3.2 SGX Elements Description
The coarse grain scheduler (CGS) is the main system controller for the POWERVR SGX architecture. It
consists of two stages, the DMS and the PDS. The DMS processes requests from the data masters and
determines which tasks can be executed given the resource requirements. The PDS then controls the
loading and processing of data on the USSE.
There are three data masters in the SGX core:
• The VDM is the initiator of transform and lighting processing within the system. The VDM reads an
184
Graphics Accelerator (SGX) SPRUH73H–October 2011–Revised April 2013
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