UART Registers
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19.5.1.35 Divisor Latches Low Register (DLL)
The divisor latches low register (DLL) with the DLH register stores the 14-bit divisor for generation of the
baud clock in the baud rate generator. DLH stores the most-significant part of the divisor, DLL stores the
least-significant part of the divisor. The DLL register is shown in Figure 19-68 and described in Table 19-
66.
NOTE: DLL and DLH can be written to only before sleep mode is enabled (before IER[4] is set).
Figure 19-68. Divisor Latches Low Register (DLL)
15 8 7 0
Reserved CLOCK_LSB
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-66. Divisor Latches Low Register (DLL) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved.
7-0 CLOCK_LSB 0-FFh Divisor latches low. Stores the 8 LSB divisor value.
19.5.1.36 Divisor Latches High Register (DLH)
The divisor latches high register (DLH) with the DLL register stores the 14-bit divisor for generation of the
baud clock in the baud rate generator. DLH stores the most-significant part of the divisor, DLL stores the
least-significant part of the divisor. The DLH register is shown in Figure 19-69 and described in Table 19-
67.
NOTE: DLL and DLH can be written to only before sleep mode is enabled (before IER[4] is set).
Figure 19-69. Divisor Latches High Register (DLH)
15 6 5 0
Reserved CLOCK_MSB
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-67. Divisor Latches High Register (DLH) Field Descriptions
Bit Field Value Description
15-6 Reserved 0 Reserved.
5-0 CLOCK_MSB 0-3Fh Divisor latches high. Stores the 6 MSB divisor value.
3536
Universal Asynchronous Receiver/Transmitter (UART) SPRUH73H–October 2011–Revised April 2013
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