EMIF
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7.3.5.38 RD_WR_EXEC_THRSH Register (offset = 120h) [reset = 0h]
Read Write Execution Threshold Register
Read Write Execution Threshold Register is shown in Figure 7-128 and described in Table 7-148.
Figure 7-128. Read Write Execution Threshold Register
31 30 29 28 27 26 25 24
Reserved
R-
23 22 21 20 19 18 17 16
Reserved
R-
15 14 13 12 11 10 9 8
Reserved REG_WR_THRSH
R- R/W-
7 6 5 4 3 2 1 0
Reserved REG_RD_THRSH
R- R/W-
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-148. Read Write Execution Threshold Register Field Descriptions
Bit Field Type Reset Description
31-13 Reserved R
Reserved.
12-8 REG_WR_THRSH R/W Write Threshold.
Number of SDRAM write bursts after which the EMIF arbitration will
switch to executing read commands.
The value programmed is always minus one the required number.
7-5 Reserved R
Reserved.
4-0 REG_RD_THRSH R/W Read Threshold.
Number of SDRAM read bursts after which the EMIF arbitration will
switch to executing write commands.
The value programmed is always minus one the required number.
466
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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