GPIO Registers
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25.4.1.2 GPIO_SYSCONFIG Register (offset = 10h) [reset = 0h]
GPIO_SYSCONFIG is shown in Figure 25-8 and described in Table 25-7.
The GPIO_SYSCONFIG register controls the various parameters of the L4 interconnect. When the
AUTOIDLE bit is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in
sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command has a 2
OCP cycle latency.
Figure 25-8. GPIO_SYSCONFIG Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved IDLEMODE ENAWAKEUP SOFTRESET AUTOIDLE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 25-7. GPIO_SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
31-5 Reserved R 0h
4-3 IDLEMODE R/W 0h
Power Management, Req/Ack control.
0x0 = Force-idle. An idle request is acknowledged unconditionally
0x1 = No-idle. An idle request is never acknowledged
0x2 = Smart-idle. Acknowledgment to an idle request is given based
on the internal activity of the module
0x3 = Smart Idle Wakeup (GPIO0 only)
2 ENAWAKEUP R/W 0h
0x0 = Wakeup generation is disabled.
0x1 = Wakeup capability is enabled upon expected transition on
input GPIO pin.
1 SOFTRESET R/W 0h Software reset.
This bit is automatically reset by the hardware.
During reads, it always returns 0.
0x0 = Normal mode
0x1 = The module is reset
0 AUTOIDLE R/W 0h
Internal interface clock gating strategy
0x0 = Internal Interface OCP clock is free-running
0x1 = Automatic internal OCP clock gating, based on the OCP
interface activity
4070
General-Purpose Input/Output SPRUH73H–October 2011–Revised April 2013
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