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EDMA3 Registers
11.4.1.5.3 Memory Protection Fault Command Register (MPFCR)
The memory protection fault command register (MPFCR) is shown in Figure 11-68 and described in
Table 11-52.
Figure 11-68. Memory Protection Fault Command Register (MPFCR)
31 16
Reserved
R-0
15 1 0
Reserved MPFCLR
R-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-52. Memory Protection Fault Command Register (MPFCR) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
0 MPFCLR Fault clear register.
0 CPU write of 0 has no effect.
1 CPU write of 1 to the MPFCLR bit causes any error conditions stored in the memory protection fault
address register (MPFAR) and the memory protection fault status register (MPFSR) to be cleared.
967
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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