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Table 14-5. GMII Interface Signal Descriptions in GIG (1000Mbps) Mode (continued)
Signal Type Description
In full-duplex operation, the MCOL pin is used for hardware transmit flow control.
Asserting the MCOL pin will stop packet transmissions; packets in the process of
MCOL I
being transmitted when MCOL is asserted will complete transmission. The MCOL
pin should be held low if hardware transmit flow control is not used.
MCRS I In full-duplex operation, the MCRS pin should be held low.
The receive clock is a continuous clock that provides the timing reference for
receive operations. The MRXD,MRXDV, and MRXER signals are tied to this
MRCLK I
clock.The clock is generated by the PHY and is 125 MHz at 1000Mbps of
operation.
The receive data pins are a collection of 8 data signals comprising 8 bits of
MRXD I data.MRXD0 is the least-significant bit (LSB).The signals are synchronized by
MRCLK and valid only when MRXDV is asserted.
The receive data valid signal indicates that the MRXD pins are generating byte
MRXDV I
data for use by the 3PSW. It is driven synchronously to MRCLK.
Management data clock (MDIO_CLK). The MDIO data clock is sourced by the
MDCLK O MDIO module on the system. It is used to synchronize MDIO data access
operations done on the MDIO pin.
MDIO DATA(MDI0_D). MDIO data pin drives PHY management data into and
out of the PHY by way of an access frame consisting of start of frame, read/write
MDIO I/O indication,PHY address, register address, and data bit cycles. The MDIO_D pin
acts as an output for all but the data bit cycles at which time it is an input for read
operations.
14.2.5.2
Table 14-6. GMII Interface Signal Descriptions in MII (100/10Mbps) Mode
Signal Type Description
GMTCLK O
The clock is generated by the CPSW and is running at 125 MHz
The transmit clock is a continuous clock that provides the timing reference for
transmit operations. The MTXD and MTXEN signals are tied to this clock. The
MtCLK I
clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz
at 100 Mbps operation.
MTXD[7-4] pins of MTXD data are not used.The transmit data pins are a
collection of 4 data signals MTXD[3-0] comprising 4 bits of data. MTXD0 is the
Mtxd O
least-significant bit (LSB). The signals are synchronized by MTCLK and valid
only when MTXEN is asserted.
The transmit enable signal indicates that the MTXD pins are generating 4bit data
Mtxen O
for use by the PHY. It is driven synchronously by MTCLK.
In half-duplex operation, the MCOL pin is asserted by the PHY when it detects a
collision on the network. It remains asserted while the collision condition
persists.This signal is not necessarily synchronous to MTCLK nor MRCLK.
MCOL I In full-duplex operation, the MCOL pin is used for hardware transmit flow control.
Asserting the MCOL pin will stop packet transmissions; packets in the process of
being transmitted when MCOL is asserted will complete transmission. The MCOL
pin should be held low if hardware transmit flow control is not used
In half-duplex operation, the MCRS pin is asserted by the PHY when the network
is not idle in either transmit or receive. The pin is deasserted when both transmit
MCRS I and receive are idle. This signal is not necessarily synchronous to MTCLK nor
MRCLK.
In full-duplex operation, the MCRS pin should be held low.
The receive clock is a continuous clock that provides the timing reference for
receive operations. The MRXD, MRXDV, and MRXER signals are tied to this
MRCLK I
clock. The clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation
and 25 MHz at 100 Mbps operation.
MRXD[7-4] bits are unused in the MII mode.The receive data pins are a
collection of 4 data signals comprising 4 bits of data.MRXD0 is the least-
MRXD I
significant bit (LSB).The signals are synchronized by MRCLK and valid only
when MRXDV is asserted.
1172
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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