DMTimer
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20.1.5.15 TCAR1 Register (offset = 50h) [reset = 0h]
TCAR1 is shown in Figure 20-23 and described in Table 20-25.
When the appropriate (rising, falling or both) transition is detected in the edge detection logic the current
counter value is stored to the TCAR1 register. Note that since the OCP clock is completely asynchronous
with the timer clock, some synchronization is done in order to make sure that the TCAR1 value is not read
while it is being updated due to some capture event. In 16-bit mode the following sequence must be
followed to read the TCAR1 register properly:
Figure 20-23. TCAR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPTURED_VALUE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-25. TCAR1 Register Field Descriptions
Bit Field Type Reset Description
31-0 CAPTURED_VALUE R/W 0h
Timer counter value captured on an external event trigger
3582
Timers SPRUH73H–October 2011–Revised April 2013
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