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Ethernet Subsystem Registers
14.5.3.2 CPTS_CONTROL Register (offset = 4h) [reset = 0h]
CPTS_CONTROL is shown in Figure 14-79 and described in Table 14-91.
TIME SYNC CONTROL REGISTER
Figure 14-79. CPTS_CONTROL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved HW4_TS_PUSH_EN HW3_TS_PUSH_EN HW2_TS_PUSH_EN HW1_TS_PUSH_EN
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved INT_TEST CPTS_EN
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-91. CPTS_CONTROL Register Field Descriptions
Bit Field Type Reset Description
31-12 Reserved R 0h
11 HW4_TS_PUSH_EN R/W 0h
Hardware push 4 enable
10 HW3_TS_PUSH_EN R/W 0h
Hardware push 3 enable
9 HW2_TS_PUSH_EN R/W 0h
Hardware push 2 enable
8 HW1_TS_PUSH_EN R/W 0h
Hardware push 1 enable
7-2 Reserved R 0h
1 INT_TEST R/W 0h Interrupt Test - When set, this bit allows the raw interrupt to be
written to facilitate interrupt test.
0 CPTS_EN R/W 0h Time Sync Enable - When disabled (cleared to zero), the RCLK
domain is held in reset.
0 - Time Sync Disabled
1 - Time Sync Enabled
1311
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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