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EMIF
7.3.5.24 READ_IDLE_CTRL_SHDW Register (offset = 9Ch) [reset = 50000h]
READ_IDLE_CTRL_SHDW is shown in Figure 7-114 and described in Table 7-134.
Figure 7-114. READ_IDLE_CTRL_SHDW Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved reg_read_idle_len_shdw
R-0h R/W-5h
15 14 13 12 11 10 9 8
Reserved reg_read_idle_interval
_shdw
R-0h R/W-0h
7 6 5 4 3 2 1 0
reg_read_idle_interval_shdw
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-134. READ_IDLE_CTRL_SHDW Register Field Descriptions
Bit Field Type Reset Description
31-20 Reserved R 0h
19-16 reg_read_idle_len_shdw R/W 5h Shadow field for reg_read_idle_len.
This field is loaded into reg_read_idle_len field in Read Idle Control
register when SIdleAck is asserted
15-9 Reserved R 0h
8-0 reg_read_idle_interval_sh R/W 0h Shadow field for reg_read_idle_interval.
dw This field is loaded into reg_read_idle_interval field in Read Idle
Control register when SIdleAck is asserted.
449
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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