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Ethernet Subsystem Registers
14.5.6.39 P2_PORT_VLAN Register (offset = 214h) [reset = 0h]
P2_PORT_VLAN is shown in Figure 14-159 and described in Table 14-174.
CPSW PORT 2 VLAN REGISTER
Figure 14-159. P2_PORT_VLAN Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
PORT_PRI PORT_CFI PORT_VID
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PORT_VID
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-174. P2_PORT_VLAN Register Field Descriptions
Bit Field Type Reset Description
15-13 PORT_PRI R/W 0h
Port VLAN Priority (7 is highest priority)
12 PORT_CFI R/W 0h
Port CFI bit
11-0 PORT_VID R/W 0h
Port VLAN ID
1397
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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