USB Registers
www.ti.com
16.5.5.4 TXGCR0 Register (offset = 800h) [reset = 0h]
TXGCR0 is shown in Figure 16-155 and described in Table 16-167.
Figure 16-155. TXGCR0 Register
31 30 29 28 27 26 25 24
TX_ENABLE TX_TEARDOWN Reserved
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved TX_DEFAULT_QMGR TX_DEFAULT_QNUM
W-0h W-0h
7 6 5 4 3 2 1 0
TX_DEFAULT_QNUM
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-167. TXGCR0 Register Field Descriptions
Bit Field Type Reset Description
31 TX_ENABLE R/W 0h This field enables or disables the channel
0 = channel is disabled
1 = channel is enabled This field will be cleared after a channel
teardown is complete.
30 TX_TEARDOWN R/W 0h Setting this bit will request the channel to be torn down.
This field will remain set after a channel teardown is complete.
13-12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be
used to queue teardown descriptors back to the host.
11-0 TX_DEFAULT_QNUM W 0h This field controls the default queue number within the selected
queue manager onto which teardown descriptors will be queued
back to the host.
Table
98 -Tx Channel N Global Configuration Registers
1932
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
