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Power, Reset, and Clock Management
8.1.12.3.5 CM_MAC_CLKSEL Register (offset = 14h) [reset = 4h]
CM_MAC_CLKSEL is shown in Figure 8-142 and described in Table 8-151.
Selects the clock divide ration for MII clock [warm reset insensitive]
Figure 8-142. CM_MAC_CLKSEL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MII_CLK_SEL Reserved
R-0h R/W-1h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-151. CM_MAC_CLKSEL Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 MII_CLK_SEL R/W 1h MII Clock Divider Selection.
This bit is warm reset insensitive when CPSW RESET_ISO is
enabled
0x0 = SEL0 : Selects 1/2 divider of SYSCLK2
0x1 = SEL1 : Selects 1/5 divide ratio of SYSCLK2
1-0 Reserved R 0h
679
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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