Functional Description
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Table 19-10. Local Power-Management Features
Feature Registers Description
Clock autogating UART_SYSC[0] AUTOIDLE This bit allows local power optimization in the module by gating the
UARTi_ICLK clock on interface activity or gating the UARTi_FCLK
clock on internal activity.
Slave idle modes UART_SYSC[4:3] IDLEMODE Force-idle, no-idle, smart-idle, and smart-idle wakeup-capable modes
are available
Clock activity N/A Feature not available
Master standby N/A Feature not available
modes
Global wake-up UART_SYSC[2] ENAWAKEUP This bit enables the wake-up feature at module level.
enable
Wake-Up sources N/A Feature not available
enable
19.3.5 Interrupt Requests
The UART IrDA CIR module generates interrupts. All interrupts can be enabled/disabled by writing to the
appropriate bit in the interrupt enable register (IER). The interrupt status of the device can be checked at
any time by reading the interrupt identification register (IIR). The UART, IrDA, and CIR modes have
different interrupts in the UART IrDA CIR module and therefore have different IER and IIR mappings
according to the selected mode.
19.3.5.1 UART Mode Interrupt Management
19.3.5.1.1 UART Interrupts
UART mode includes seven possible interrupts prioritized to six levels.
When an interrupt is generated, the interrupt identification register (UARTi.UART_IIR) sets the
UARTi.UART_IIR[0] IT_PENDING bit to 0 to indicate that an interrupt is pending, and indicates the type of
interrupt through the UARTi.UART_IIR[5:1] bit field. Table 19-11 summarizes the interrupt control
functions.
Table 19-11. UART Mode Interrupts
UART_IIR[5:0] Priority Level Interrupt Type Interrupt Source Interrupt Reset Method
000001 None None None None
000110 1 Receiver line OE, FE, PE, or BI errors occur in FE, PE, BI: Read the UART_RHR
status characters in the RX FIFO. register. OE: Read the UART_LSR
register.
001100 2 RX time-out Stale data in RX FIFO Read the UART_RHR register.
000100 2 RHR interrupt DRDY (data ready) (FIFO Read the UART_RHR register until the
disable) interrupt condition disappears.
RX FIFO above trigger level
(FIFO enable)
000010 3 THR interrupt TFE (UART_THR empty) (FIFO Write to the UART_THR until the
disable) interrupt condition disappears.
TX FIFO below trigger level (FIFO
enable)
000000 4 Modem status See the UART_MSR register. Read the UART_MSR register.
010000 5 XOFF Receive XOFF characters/special Receive XON character(s), if XOFF
interrupt/special character interrupt/read of the UART_IIR register,
character if special character interrupt.
interrupt
100000 6 CTS, RTS, DSR RTS pin or CTS pin or DSR Read the UART_IIR register.
change state from active (low) to
inactive (high).
3456
Universal Asynchronous Receiver/Transmitter (UART) SPRUH73H–October 2011–Revised April 2013
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