Multimedia Card Registers
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18.5.1.6 SD_PWCNT Register (offset = 130h) [reset = 0h]
SD_PWCNT is shown in Figure 18-42 and described in Table 18-25.
This register is used to program a mmc counter to delay command transfers after activating the PAD
power, this value depends on PAD characteristics and voltage.
Figure 18-42. SD_PWCNT Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PWRCNT
R/W-0h
7 6 5 4 3 2 1 0
PWRCNT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-25. SD_PWCNT Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-0 PWRCNT R/W 0h Power counter register.
This register is used to introduce a delay between the PAD ACTIVE
pin assertion and the command issued.
0x0 = No additional delay added
0x1 = TCF delay (card clock period)
0x2 = TCF x 2 delay (card clock period)
0xfffe = TCF x 65534 delay (card clock period)
0xffff = TCF x 65535 delay (card clock period)
3402
Multimedia Card (MMC) SPRUH73H–October 2011–Revised April 2013
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