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WATCHDOG
20.4.4.1.12 WDT_WSPR Register (offset = 48h) [reset = 0h]
WDT_WSPR is shown in Figure 20-110 and described in Table 20-123.
The Watchdog Start/Stop Register holds the start-stop value that controls the internal start-stop FSM.
Figure 20-110. WDT_WSPR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WSPR_VALUE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-123. WDT_WSPR Register Field Descriptions
Bit Field Type Reset Description
31-0 WSPR_VALUE R/W 0h
Value of the start-stop register
3693
SPRUH73H–October 2011–Revised April 2013 Timers
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