WATCHDOG
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20.4.4.1.11 WDT_WDLY Register (offset = 44h) [reset = 0h]
WDT_WDLY is shown in Figure 20-109 and described in Table 20-122.
The Watchdog Delay Configuration Register holds the delay value that controls the internal pre-overflow
event detection.
Figure 20-109. WDT_WDLY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLY_VALUE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-122. WDT_WDLY Register Field Descriptions
Bit Field Type Reset Description
31-0 WDLY_VALUE R/W 0h
Value of the delay register
3692
Timers SPRUH73H–October 2011–Revised April 2013
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