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DMTimer 1ms
20.2.5.1 TIDR Register (offset = 0h) [reset = 15h]
TIDR is shown in Figure 20-35 and described in Table 20-36.
This register contains the IP revision code
Figure 20-35. TIDR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
TID_REV
R-15h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-36. TIDR Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
Reads return 0
7-0 TID_REV R 15h IP revision [
7:4] Major revision [
3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1
3599
SPRUH73H–October 2011–Revised April 2013 Timers
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