DMTimer 1ms
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Table 20-35. DMTIMER_1MS REGISTERS (continued)
Offset Acronym Register Name Section
28h TCRR This register holds the value of the internal counter Section 20.2.5.8
2Ch TLDR This register holds the timer's load value Section 20.2.5.9
30h TTGR This register triggers a counter reload of timer by writing Section 20.2.5.10
any value in it.
34h TWPS This register contains the write posting bits for all writ- Section 20.2.5.11
able functional registers
38h TMAR This register holds the match value to be compared with Section 20.2.5.12
the counter's value
3Ch TCAR1 This register holds the value of the first counter register Section 20.2.5.13
capture
40h TSICR Timer Synchronous Interface Control Register Section 20.2.5.14
44h TCAR2 This register holds the value of the second counter Section 20.2.5.15
register capture
48h TPIR This register is used for 1ms tick generation. Section 20.2.5.16
The TPIR register holds the value of the positive
increment.
The value of this register is added with the value of the
TCVR to define whether next value loaded in TCRR will
be the sub-period value or the over-period value.
4Ch TNIR This register is used for 1ms tick generation. Section 20.2.5.17
The TNIR register holds the value of the negative
increment.
The value of this register is added with the value of the
TCVR to define whether next value loaded in TCRR will
be the sub-period value or the over-period value.
50h TCVR This register is used for 1ms tick generation. Section 20.2.5.18
The TCVR register defines whether next value loaded in
TCRR will be the sub-period value or the over-period
value.
54h TOCR This register is used to mask the tick interrupt for a Section 20.2.5.19
selected number of ticks.
58h TOWR This register holds the number of masked overflow Section 20.2.5.20
interrupts.
3598
Timers SPRUH73H–October 2011–Revised April 2013
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