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EMIF
7.3.5.26 IRQSTATUS_SYS Register (offset = ACh) [reset = 0h]
IRQSTATUS_SYS is shown in Figure 7-116 and described in Table 7-136.
Figure 7-116. IRQSTATUS_SYS Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved reg_ta_sys reg_err_sys
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-136. IRQSTATUS_SYS Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 Reserved R/W 0h
Reserved.
1 reg_ta_sys R/W 0h Enabled status of system OCP interrupt.
Write 1 to clear the status after interrupt has been serviced (raw
status gets cleared, i.e.
even if not enabled).
Writing a 0 has no effect.
0 reg_err_sys R/W 0h Enabled status of system OCP interrupt.
Write 1 to clear the status after interrupt has been serviced (raw
status gets cleared, i.e.
even if not enabled).
Writing a 0 has no effect.
451
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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