Enhanced Capture (eCAP) Module
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15.3.4.1.12 ECFRC Register (offset = 32h) [reset = 0h]
ECFRC is shown in Figure 15-127 and described in Table 15-120.
Figure 15-127. ECFRC Register
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
CMPEQ PRDEQ CNTOVF CEVT4 CEVT3 CEVT2 CEVT1 Reserved
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-120. ECFRC Register Field Descriptions
Bit Field Type Reset Description
15-8 Reserved R 0h
7 CMPEQ R/W 0h
Force Counter Equal Compare Interrupt
0x0 = No effect. Always reads back a 0.
0x1 = Writing a 1 sets the CMPEQ flag bit.
6 PRDEQ R/W 0h
Force Counter Equal Period Interrupt
0x0 = No effect. Always reads back a 0.
0x1 = Writing a 1 sets the PRDEQ flag bit.
5 CNTOVF R/W 0h
Force Counter Overflow
0x0 = No effect. Always reads back a 0.
0x1 = Writing a 1 to this bit sets the CNTOVF flag bit.
4 CEVT4 R/W 0h
Force Capture Event 4
0x0 = No effect. Always reads back a 0.
0x1 = Writing a 1 sets the CEVT4 flag bit
3 CEVT3 R/W 0h
Force Capture Event 3
0x0 = No effect. Always reads back a 0.
0x1 = Writing a 1 sets the CEVT3 flag bit
2 CEVT2 R/W 0h
Force Capture Event 2
0x0 = No effect. Always reads back a 0.
0x1 = Writing a 1 sets the CEVT2 flag bit.
1 CEVT1 R/W 0h Always reads back a 0.
Force Capture Event 1
0x0 = No effect.
0x1 = Writing a 1 sets the CEVT1 flag bit.
0 Reserved R 0h
1648
Pulse-Width Modulation Subsystem (PWMSS) SPRUH73H–October 2011–Revised April 2013
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