Power, Reset, and Clock Management
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8.1.12.2.13 CM_AUTOIDLE_DPLL_DDR Register (offset = 30h) [reset = 0h]
CM_AUTOIDLE_DPLL_DDR is shown in Figure 8-96 and described in Table 8-104.
This register provides automatic control over the DPLL activity.
Figure 8-96. CM_AUTOIDLE_DPLL_DDR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved AUTO_DPLL_MODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-104. CM_AUTOIDLE_DPLL_DDR Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2-0 AUTO_DPLL_MODE R/W 0h
AUTO_DPLL_MODE is not supported.
628
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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