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7.3.5.6 SDRAM_REF_CTRL_SHDW Register (offset = 14h) [reset = 0h]
SDRAM_REF_CTRL_SHDW is shown in Figure 7-96 and described in Table 7-116.
Figure 7-96. SDRAM_REF_CTRL_SHDW Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
reg_refresh_rate_shdw
R/W-0h
7 6 5 4 3 2 1 0
reg_refresh_rate_shdw
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-116. SDRAM_REF_CTRL_SHDW Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-0 reg_refresh_rate_shdw R/W 0h Shadow field for reg_refresh_rate.
This field is loaded into reg_refresh_rate field in SDRAM Refresh
Control register when SIdleAck is asserted.
This register is not auto corrected when the value is invalid.
430
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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