EDMA3 Registers
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11.4.1.1.6 DMA Channel Queue n Number Registers (DMAQNUMn)
The DMA channel queue number register (DMAQNUMn) allows programmability of each of the 64 DMA
channels in the EDMA3CC to submit its associated synchronization event to any event queue in the
EDMA3CC. At reset, all channels point to event queue 0.
The DMAQNUMn is shown in Figure 11-47 and described in Table 11-31. Table 11-32 shows the
channels and their corresponding bits in DMAQNUMn.
NOTE: Because the event queues in EDMA3CC have a fixed association to the transfer controllers,
that is, Q0 TRs are submitted to TC0, Q1 TRs are submitted to TC1, etc., by programming
DMAQNUMn for a particular DMA channel n also dictates which transfer controller is utilized
for the data movement (or which EDMA3TC receives the TR request).
Figure 11-47. DMA Channel Queue n Number Registers (DMAQNUMn)
31 30 28 27 26 24 23 22 20 19 18 16
Rsvd En Rsvd En Rsvd En Rsvd En
R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 R-0 R/W-0
15 14 12 11 10 8 7 6 4 3 2 0
Rsvd En Rsvd En Rsvd En Rsvd En
R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-31. DMA Channel Queue n Number Registers (DMAQNUMn) Field Descriptions
Bit Field Value Description
31-0 En 0-7h DMA queue number. Contains the event queue number to be used for the corresponding DMA channel.
Programming DMAQNUMn for an event queue number to a value more then the number of queues
available in the EDMA3CC results in undefined behavior.
0 Event n is queued on Q0.
1h Event n is queued on Q1.
2h Event n is queued on Q2.
3h Event n is queued on Q3.
4h-7h Reserved.
Table 11-32. Bits in DMAQNUMn
Channel Number (DMAQNUMn)
En bit 0 1 2 3 4 5 6 7
0-2 E0 E8 E16 E24 E32 E40 E48 E56
4-6 E1 E9 E17 E25 E33 E41 E49 E57
8-10 E2 E10 E18 E26 E34 E42 E50 E58
12-14 E3 E11 E19 E27 E35 E43 E51 E59
16-18 E4 E12 E20 E28 E36 E44 E52 E60
20-22 E5 E13 E21 E29 E37 E45 E53 E61
24-26 E6 E14 E22 E30 E38 E46 E54 E62
28-30 E7 E15 E23 E31 E39 E47 E55 E63
11.4.1.1.7 QDMA Channel Queue Number Register (QDMAQNUM)
The QDMA channel queue number register (QDMAQNUM) is used to program all the QDMA channels in
the EDMA3CC to submit the associated QDMA event to any of the event queues in the EDMA3CC.
The QDMAQNUM is shown in Figure 11-48 and described in Table 11-33.
948
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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