EMIF
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7.3.5.15 INT_CONFIG Register (offset = 54h) [reset = 0h]
Interface Configuration Register
Interface Configuration Register is shown in Figure 7-105 and described in Table 7-125.
Figure 7-105. Interface Configuration Register
31 30 29 28 27 26 25 24
Reserved
R-0
23 22 21 20 19 18 17 16
REG_COS_COUNT_1
R/W-FF
15 14 13 12 11 10 9 8
REG_COS_COUNT_2
R/W-FF
7 6 5 4 3 2 1 0
REG_PR_OLD_COUNT
R/W-FF
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-125. Interface Configuration Register Field Descriptions
Bit Field Type Reset Description
31-24 Reserved R R
Reserved for future use.
23-16 REG_COS_COUNT_1 R/W 0xFF Priority Raise Counter for class of service 1.
Number of m_clk cycles after which the EMIF momentarily raises the
priority of the class of service 1 commands in the Command FIFO.
A value of N will be equal to N x 16 clocks.
15-8 REG_COS_COUNT_2 R/W 0xFF Priority Raise Counter for class of service 2.
Number of m_clk cycles after which the EMIF momentarily raises the
priority of the class of service 2 commands in the Command FIFO.
A value of N will be equal to N x 16 clocks.
7-0 REG_PR_OLD_COUNT R/W 0xFF Priority Raise Old Counter.
Number of m_clk cycles after which the EMIF momentarily raises the
priority of the oldest command in the OCP Command FIFO.
A value of N will be equal to N x 16 clocks.
440
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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