Ethernet Subsystem Registers
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14.5.8.4 STAT_PORT_EN Register (offset = Ch) [reset = 0h]
STAT_PORT_EN is shown in Figure 14-187 and described in Table 14-204.
STATISTICS PORT ENABLE REGISTER
Figure 14-187. STAT_PORT_EN Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved P2_STAT_EN P1_STAT_EN P0_STAT_EN
R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-204. STAT_PORT_EN Register Field Descriptions
Bit Field Type Reset Description
2 P2_STAT_EN R/W-0 0 Port 2 (GMII2 and Port 2 FIFO) Statistics Enable
0 - Port 2 statistics are not enabled.
1 - Port 2 statistics are enabled.
1 P1_STAT_EN R/W-0 0 Port 1 (GMII1 and Port 1 FIFO) Statistics Enable
0 - Port 1 statistics are not enabled.
1 - Port 1 statistics are enabled.
0 P0_STAT_EN R/W-0 0 Port 0 Statistics Enable
0 - Port 0 statistics are not enabled
1 - Port 0 statistics are enabled.
FIFO overruns (SOFOVERRUNS) are the only port 0 statistics that
are enabled to be kept.
1428
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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