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7.3.5.23 READ_IDLE_CTRL Register (offset = 98h) [reset = 50000h]
READ_IDLE_CTRL is shown in Figure 7-113 and described in Table 7-133.
Figure 7-113. READ_IDLE_CTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved reg_read_idle_len
R-0h R/W-5h
15 14 13 12 11 10 9 8
Reserved reg_read_idle_interval
R-0h R/W-0h
7 6 5 4 3 2 1 0
reg_read_idle_interval
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-133. READ_IDLE_CTRL Register Field Descriptions
Bit Field Type Reset Description
31-20 Reserved R 0h
19-16 reg_read_idle_len R/W 5h
The Read Idle Length field determines the minimum size
(reg_read_idle_len-1 clock cycles) of Read Idle window for the read
idle detection as well as the force read idle time.
15-9 Reserved R 0h
8-0 reg_read_idle_interval R/W 0h The Read Idle Interval field determines the maximum interval
((reg_read_idle_interval-1)*64 clock cycles) between read idle
detections or force.
A value of zero disables the read idle function.
448
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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