Ethernet Subsystem Registers
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14.5.6.2 P0_MAX_BLKS Register (offset = 8h) [reset = 104h]
P0_MAX_BLKS is shown in Figure 14-122 and described in Table 14-137.
CPSW PORT 0 MAXIMUM FIFO BLOCKS REGISTER
Figure 14-122. P0_MAX_BLKS Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved P0_TX_MAX_BLKS
R/W-10h
7 6 5 4 3 2 1 0
P0_TX_MAX_BLKS P0_RX_MAX_BLKS
R/W-10h R/W-4h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-137. P0_MAX_BLKS Register Field Descriptions
Bit Field Type Reset Description
8-4 P0_TX_MAX_BLKS R/W 10h Transmit FIFO Maximum Blocks - This value is the maximum
number of 1k memory blocks that may be allocated to the FIFO's
logical transmit priority queues.
0x10 is the recommended value of p0_tx_max_blks.
Port 0 should remain in flow control mode.
0xe is the minimum value tx max blks.
3-0 P0_RX_MAX_BLKS R/W 4h Receive FIFO Maximum Blocks - This value is the maximum number
of 1k memory blocks that may be allocated to the FIFO's logical
receive queue.
0x4 is the recommended value.
0x3 is the minimum value rx max blks and 0x6 is the maximum
value.
1358
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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